Memory access control apparatus

ABSTRACT

In a microcomputer system with an asynchronous working central processing unit (CPU) and a cathode ray tube (CRT) display, a memory access control apparatus includes a memory, particularly a video RAM, a CRT controller connected to the CRT for accessing the memory, a system clock for generating system clock pulses which are supplied to the CPU, a multiplexing clock for generating multiplexing clock signals based on the system clock and having a frequency which is one-half the frequency of the system clock pulses, and a multiplexer connected to the CPU and the CRT controller through which the CPU and the CRT controller selectively access the memory in a time sharing manner according to the multiplexing clock signals.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a microcomputer apparatus, and moreparticularly, to a memory accessing control apparatus that permits acentral processing unit and a cathode ray tube controller to access amemory in a time sharing manner.

2. Description of the Prior Art

In microcomputer systems, the output is frequently displayed on acathode ray tube (CRT). The data to be displayed can be stored in avideo-random access memory (video-RAM) which is accessed by a CRTcontroller in a direct memory access (DMA) operation.

The central processing unit (CPU) supplies the data to the video-RAM fordisplay. The CRT can flicker if the CPU accesses the video-RAM at thesame time that the CRT controller tries to access the video-RAM in a DMAoperation. The flicker on the screen of the CRT is undesirable anddetracts from the operation of the microcomputer system.

Various methods have been suggested to avoid flickering of the CRT. Inone method, the CPU accesses the video-RAM during the fly-back period ofthe CRT scan when the CRT controller does not access the video-RAM. Inanother prior art method, the CRT controller and the CPU access thevideo-RAM in a time sharing manner. In a third prior art method, the CPUcycle-steals with respect to the CRT controller, so that the CRTdisplays the same data for an extended period of time.

The suggested methods a not completely satisfactory in dealing with theflicker problem of the CRT. According to the first method, the CPUprocessing must be interrupted so that it can access the video-RAMduring the fly-back period of the CRT scan. When the CPU and the CRTcontroller have time sharing access to the video-RAM, a high speed RAMis required. If the system clock frequency is 4 MHz, the video-RAM musthave an access time of about 50 n. sec. The cycle-stealing method can beimplemented most easily with a synchronous working CPU such as a6800-type, in which the machine cycles are equally timed from one clock.It is quite difficult to implement a cycle-stealing operation with anasynchronous working CPU, such as Zilog, Inc. models 8080 or ZOA, inwhich various machine cycles have different numbers of clock pulsesallocated thereto.

OBJECTS AND SUMMARY OF THE INVENTION

It is an object of the present invention to provide a novel memoryaccessing apparatus for use in a microcomputer system.

It is a further object of the present invention to provide a memoryaccessing apparatus in which a cathode ray tube controller and a centralprocessing unit access a random access memory in a time sharing manner.

It is yet another object of the present invention to provide a memorycontrol apparatus which permits an asynchronous working centralprocessing unit and a cathode ray tube controller selectively to accessa random access memory.

In accordance with one aspect of the present invention, a memory accesscontrol apparatus used in combination with an asynchronous centralprocessing unit includes an addressable memory, a controller foraccessing the memory, and a multiplexer through which the centralprocessing unit and the controller selectively access the memory in atime sharing manner. In a preferred embodiment, the memory is avideo-random access memory which can be allocated to an I/O port of thecentral processing unit, so that the central processing unit accessesthe I/O port in a time-sharing manner.

The above, and other objects, features and advantages of the inventionwill be apparent from the follwing detailed description of anillustrative embodiment thereof which is to be read in connection withthe accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a microcomputer apparatus for use with thepresent invention;

FIG. 2 is a block diagram of a memory access control apparatus accordingto one embodiment of this invention;

FIG. 3 is a detailed block diagram of a portion of the memory accesscontrol apparatus of FIG. 2;

FIGS. 4A and 4B are timing charts illustrating the timing of a centralprocessing unit accessing an input/output device in accordance with thepresent invention;

FIG. 5A is a schematic diagram used to explain the memory accessallocation of a random access memory and a read only memory;

FIGS. 5B and 5C are schematic diagrams used to explain the memoryaddress allocation of a video-random access memory used in accordancewith the present invention;

FIG. 6 is a schematic diagram used to explain the display of an image ona screen of a cathode ray tube from data stored in the video-randomaccess memory of FIGS. 5B and 5C;

FIG. 7 is a schematic diagram used to explain how data of four bits areallocated to one dot in the video-random access memory of FIGS. 5B and5C;

FIGS. 8A through 8L are timing charts used to explain the time-sharingoperation of the central processing unit and the cathode ray tubecontroller in accessing the video-random access memory of FIGS. 5B and5C;

FIGS. 9A and 9B are timing charts illustrating how the centralprocessing unit accesses the video-random access memory of FIGS. 5B and5C to read data stored therein; and

FIGS. 10A and 10B are timing charts illustrating how the centralprocessing unit accesses the video-random access memory of FIGS. 5B and5C to write data therein.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to the drawings in detail, and initially to FIG. 1 thereof, amicrocomputer apparatus includes an asynchronous working centralprocessing unit (CPU) 1 which may, for example, be a Z80A-CPUmanufactured by Zilog, Inc., having a clock pulse frequency of 4 MHz.Hereinafter, any reference to CPU 1 will be directed to the Z80A-CPUwhich will be used for explanatory purposes only. The microcomputerapparatus also includes a read only memory (ROM) 2 which stores amonitor program and a BASIC interpreter program, and which, for example,includes 32K 8-bit address locations from 0000H to 7FFFH, as shown inFIG. 5A. The microcomputer apparatus also includes a random accessmemory (RAM) 3 in which a user program can be written and which alsoserves as a work area for CPU 1. As also shown on FIG. 5A, (RAM) 3 mayinclude 32K 8-bit address locations from 8000H to FFFH. It is to beappreciated that the above numbers of 8-bit address locations are onlygiven for illustrative purposes, and the invention is not limited by thespecific figures used. An 8-bit data bus 4, a lower 8-bit address bus 5Land an upper 8-bit address bus 5H are connected to corresponding dataterminals D₀ to D₇, address terminals A₀ to A₇ and address terminals A₈to A₁₅, respectively, of CPU 1, ROM 2 and RAM 3 for transferringinformation therebetween. Upper 8-bit addresses of A₈ to A₁₅ aresupplied to the B register of CPU 1, and lower 8-bit addresses of A₀ toA₇ are supplied to the C register of CPU 1. Data in the A register ofCPU 1 can be directly supplied to an input/output (I/O) address.

To control the reading of information from ROM 2 and RAM 3, CPU 1supplies a memory request signal MREQ and a read signal RD to respectiveinputs of a system controller 6 to derive a memory read signal MEMRwhich is supplied to the read terminal R of each of ROM 2 and RAM 3. Inlike manner, to perform a writing operation with respect to RAM 3, awrite signal WR is generated by CPU 1, and write signal WR and theaforementioned memory request signal MREQ are supplied to respectiveinputs of the system controller 6 to derive a memory write signal MEMWwhich is supplied to the write terminal W of RAM 3.

An input/output (I/O) port 7 is provided for connection withperipherals, such as, a keyboard 8. The data terminals D₀ to D₇ arecoupled to the data bus 4, and the address terminals A₀ to A₇ arecoupled to address bus 5L. To control the reading of information fromI/O port 7, CPU 1 supplies an I/O request signal IORQ and a read signalRD to system controller 6 to derive an I/O read signal IOR which issupplied to read terminal R of I/O port 7. In like manner, to perform awriting operation with respect to I/O port 7, CPU 1 supplies a writesignal WR and the I/O request signal IORQ to system controller 6 toderive an I/O write signal IOW which is supplied to write terminal W ofI/O port 7. The I/O port 7 may have an address of, for example, 30H toFFH.

A video-RAM 10 is provided for displaying the output of CPU 1. A videodisplay controller 20 selectively accesses video-RAM 10 in accordancewith the scanning of a CRT 9 to display on that CRT 9 the processingresults of CPU 1. Video-RAM 10 has allocated thereto addresses of 12KBrunning from OOOOH to 2 FFFH, as shown on FIG. 5B. In the embodiment ofFIG. 1, however, a Z80A-CPU is used and the embodiment of FIG. 1 maydiffer from the embodiment of FIGS. 2 to 10. With the Z80A-CPU, lower8-bit address terminals A₀ to A₇ of video-RAM 10 are connected to upper8-bit address bus 5H, while upper 8-bit address terminals A₈ to A₁₅ ofvideo-RAM 10 are connected to lower 8-bit address bus 5L. I/O readsignal IOR and I/O write signal IOW derived from system controller 6 arealso supplied to read terminal R and write terminal W of video-RAM 10,just as in I/O port 7. Data terminals D₀ to D₇ of video-RAM 10 areconnected to data bus 4.

ROM 2 and RAM 3 are allocated to the memory addresses of CPU 1, whilevideo-RAM 10 and I/O port 7 are allocated to I/O port addresses ofCPU 1. The address allocations are shown in FIGS. 5A and 5B. Withrespect to ROM 2, RAM 3, and I/O port 7, all instructions from CPU 1 canbe executed by the A register. Data in video-RAM 10 can be accessed bythe BC registers of CPU 1.

Video-RAM 10 and video display controller 20 will be described morefully with reference to FIGS. 5B and 5C. With reference to FIG. 5C,video-RAM 10 is made up of three separate RAM's, a graphic displayvideo-RAM (G-RAM), a character display video-RAM (C-RAM), and aprogrammable character generator video-RAM (PCG-RAM). The addresses fromOOOOH to 1FFFH are allocated to the G-RAM, the addresses of 2000H to27FFH are allocated to the C-RAM, and the addresses from 2800H to 2FFFHare allocated to the PCG-RAM.

As illustrated in FIG. 6, the G-RAM may display a graphic planecomprising 100 rows and 160 columns of data, and the C-RAM may display acharacter plane comprising 25 rows and 80 columns. The two planes fromthe G-RAM and the C-RAM are superimposed on each other for display on ascreen 9S of CRT 9. In the illustrated embodiment, the character of thefirst address of the G-RAM (0H address) and the character at the firstaddress of the C-RAM (2000H address) are superimposed on the upper leftcorner of screen 9S.

In FIG. 7, one byte in the G-RAM represents two dots, with four bitsallocated to one dot. One of the four bits represents the color red (R),one bit represents the color green (G), one bit represents the colorblue (B), and one bit represents the luminance (L) of the dot. Each dotcan thus be one of eight colors, and each color can be either dark orlight.

In the C-RAM, one byte represents a code for one character. In thePCG-RAM, 256 desired patterns can be expressed.

With reference to FIGS. 2 and 3, the meanings of the signals used in theillustrative embodiment are indicated as follows:

φ: a clock pulse which, in the illustrative embodiment, is 4 MHz. Asignal φ, which is the φ inverted, is the clock pulse of the CPU 1.

φ/2: A clock pulse with a frequency 1/2 that of the clock pulse φ, andsynchronized therewith. In the illustrative embodiment, φ/2 is 2 MHz.

2φ: A clock pulse with a frequency of twice the clock pulse φ andsynchronized therewith. In the illustrative embodiment, 2φ is 8 MHz.

S/L: A signal to control a shift register, in which the shift operationis performed when it is in the "H" state, and the load operation isperformed when it is in the "L" state.

OIH: A signal for controlling the input and/or output state of a dataterminal of a RAM.

GRM: A signal for decoding the address of the G-RAM utilizing addresssignals A₀ to A₁₅.

CRM: A signal for decoding the address of the C-RAM utilizing addresssignals A₀ to A₁₅.

PCG: A signal for decoding the address of the PCG-RAM utilizing addresssignals A₀ to A₁₅.

GRMS: A signal, derived from the signal GRM by windowing with thesignals φ/2 and φ which selects the data bus driver of the G-RAM when itis "L".

CRMS: A signal, derived from the signal CRM by windowing with thesignals φ and φ/2 which selects the data bus driver of the C-RAM when itis "L".

PCGS: A signal, derived from the signal PCG by windowing with thesignals φ and φ/2 which selects the data bus driver of the PCG-RAM whenit is "L".

GRMWR: A write pulse for the G-RAM.

CRMWR: A write pulse for the C-RAM.

PCGWR: A write pulse of the PCG-RAM.

VRMRD: A read signal supplied to a pair of flip-flops which is "L" whenCPU 1 reads data from video-RAM 10.

DIR: A signal to control the direction of the data buses.

In FIG. 2, a G-RAM 11, a C-RAM 12, and a PCG-RAM 13, each having outputenable terminals OE and write enable terminals WE are shown to beincluded in video-RAM 10. When the output enable terminals OE are "H",data can be read from RAMs 11, 12, and 13. When write enable terminalsWE are "L", data can be written into RAMs 11, 12 and 13.

A system clock generator 21 generates clock pulse signals φ, φ/2, 2φ,signal S/L for controlling shift registers, and signals CLK and SCLK, tobe explained more fully hereinbelow. Clock pulse signal φ is inverted byinverter 1a and supplied to CPU 1.

Clock pulse signals φ, φ/2 and 2φ from system clock generator 21 aresupplied to a time sharing bus multiplex controller 22. System controlsignals IORQ, WR, and RD from CPU 1 are supplied to time sharing busmultiplex controller 22, as are signals GRM, CRM, and PCG. Time sharingbus multiplex controller 22 generates, as its outputs, signals VRMRD,DIR, GRMWR, OIH, CRMWR, PCGWR, CRMS, GRMS and PCGS. The circuits towhich the above-mentioned signals are supplied will be described morefully hereinbelow.

A CPU interface data bus driver 23 is coupled to data terminals D₀ to D₇of CPU 1 by data bus 4. Data bus driver 23 comprises a pair of Dflip-flop circuits 23W and 23R. In a preferred embodiment, flip-flopcircuits 23W and 23R are 8-bit flip-flops. The flip-flop circuits 23Rand 23W function as a read-out port and a write-in port for G-RAM 11,C-RAM 12 and PCG-RAM 13. Write-in port 23W latches data from data bus 4of CPU 1 at the falling down edge of signal DIR, and then supplies it tovideo-RAM 10 when signal DIR is "L", as seen in FIG. 10A. Read-out port23R latches data from video-RAM 10 at the falling-down edge of clockpulse signal φ/2 and supplies the data to data bus 4 when signal VRMRDis "L".

Data bus drivers 31, 32 and 33 are coupled to G-RAM 11, C-RAM 12 andPCG-RAM 13 by data buses P₃, P₄ and P₆, respectively. Data bus drivers31, 32 and 33 are coupled to CPU interface data bus driver 23 fortransmitting data to and from RAMs 11, 12 and 13. Data bus driver 31 hasa terminal G coupled to terminal GRMS of time sharing bus multiplexcontroller 22. Data bus driver 32 has a terminal G coupled to terminalCRMS of time sharing bus multiplex controller 22. Likewise, data busdriver 33 has a terminal G coupled to terminal PCGS of time sharing busmultiplex controller 22. Data bus drivers 31, 32, 33 function as gatesfor the read and/or write operation when CPU 1 accesses RAMs 11, 12 and13 by the data buses P₁ to P₆. Time sharing bus multiplex controller 22supplies a signal DIR to terminals DIR of data bus drivers 31, 32 and 33to indicate the direction of data flow thereover.

A CRT controller 34 is supplied with clock pulse signals φ/2 from systemclock 21. CRT controller 34 accesses RAMs 11, 12 and 13 by a directmemory access (DMA) operation so that the data stored therein can bedisplayed on CRT 9. CRT controller 34 generates addresses VDA to accessRAMs 11, 12 and 13 for the display operation.

Multiplexers 41, 42 and 43 are connected to RAMs 11, 12 and 13 atterminals AB by data buses P₁, P₂ and P₃, respectively. Multiplexers 41,42 and 43 have input terminals C connected to address terminals A₀ toA₁₅ of CPU 1 by data buses 5L and 5H. Multiplexers 41, 42 and 43 alsohave CRT controller 34 connected thereto at input terminals D.Multiplexers 41, 42 and 43 alternately supply addresses from CRTcontroller 34 and CPU 1 to RAMs 11, 12 and 13 so that CRT controller 34and CPU 1 can access RAMs 11, 12 and 13 of video-RAM 10 in a timesharing manner. Multiplexers 41, 42 and 43 are supplied with clock pulsesignals φ/2 from system clock 21 as timing control signals. In apreferred embodiment, multiplexers 41, 42 and 43 permit CRT controller34 to access RAMs 11, 12 and 13 when clock pulse signal φ/2 is "H", andCPU 1 to access RAMs 11, 12 and 13 when clock pulse signal φ/2 is "L".

With reference to FIG. 6, there is an offset of 2000H betweencorresponding address locations in G-RAM 11 and C-RAM 12. When addresssignal VDA is supplied to multiplexers 41, 42 from CRT controller 34,the value of the signal is shifted by 2000H to accommodate the offset inC-RAM 12. Accordingly, G-RAM 11 and C-RAM 12 are accessed at the sametime even though CRT controller 34 supplies a single access address VDA.In the following description, and in FIG. 8, the address M representedby the signal VDA is the address indicated at controller 34, rather thanas offset or shifted at C-RAM 12.

Flip-flop circuits 51 and 52 are connected by data buses P₃ and P₄,respectively, to G-RAM 11 and C-RAM 12. In a preferred embodiment,flip-flop circuits 51, 52 are 8-bit flip-flops. Flip-flop circuit 52latches data from C-RAM 12 and uses the latched data as an address forPCG-RAM 13 to obtain therefrom a pattern corresponding to the data.Since flip-flop 52 introduces a delay in the data supplied from C-RAM12, the flip-flop circuit 51 provides a delay for the data supplied fromG-RAM 11 so that the data therefrom arrives for display at the same timeas the data from C-RAM 12.

Flip-flop 51 is coupled to a parallel input and output shift register 61which distributes one byte of graphic data (FIG. 6) into two four bitdots. A parallel input and serial output shift register 62 is connectedto PCG-RAM 13 and data bus driver 33 by bus P₆ and converts the imagesignal of a one byte character to a font signal. In a preferredembodiment, shift registers 61, 62 are 8-bit registers. The outputs ofshift registers 61, 62 are supplied to a multiplexer 63 for synthesizingthe graphic signal from shift register 61 with the character signal fromshift register 62. Multiplexer 63 produces a three primary color signalin which the graphic and character planes illustrated in FIG. 6 arecombined and displayed on CRT 9.

Shift registers 61, 62 are supplied with shift register signals S/L fromsystem clock 21. Signal CLK from system clock 21 is supplied toflip-flops 51, 52 and shift register 62. Signal SCLK from system clock21 is supplied to shift register 61.

In FIG. 3, multiplexer 43 depicted in FIG. 2 comprises threemultiplexers 431, 432, 433. Addresses A₈ to A₁₁ from address bus 5H aresupplied to input terminals 1A to 4A of multiplexer 431. Address bitsA₁₂ to A₁₅ are supplied to input terminals 1A to 4A of multiplexer 432.Address bits A₀ to A₂ are supplied to input terminals 1A to 3A ofmultiplexer 433. Data bits D₀ to D₇ from C-RAM 12 and DMA address VDAare supplied through flip-flop 52 to inputs of multiplexers 431, 432,433 in a time-sharing manner. Data bits D₀ are supplied to inputterminal 4B of multiplexer 431. Data bits D₁ to D₄ are supplied toterminals 1B to 4B of multiplexer 432. Data bits D₅ to D₇ are suppliedto terminals 1B to 3B of the multiplexer 433. DMA address VDA includesraster addresses RA₀ to RA₂ supplied to input terminals 1B to 3B ofmultiplexer 431. Clock pulse signal φ/2 is supplied to input terminals Sof multiplexers 431, 432, 433.

Address bits A₀ to A₃ are supplied from output terminals 1Y to 4Y ofmultiplexer 431 to the input terminals A₀ to A₃ of PCG-RAM 13. Addressbits A₄ to A₇ are supplied from output terminals 1Y to 4Y of multiplexer432 to input terminals A₄ to A₇ of PCG-RAM 13. Address bits A₈ to A₁₀are supplied from output terminals 1Y to 3Y of multiplexer 433 to inputterminals A₈ to A₁₀ of PCG-RAM 13.

Time sharing bus multiplexer controller 22 has input thereto, as seen onthe right hand side of FIG. 3, input signals φ, φ/2, 2φ , IORQ, RD, WR,GRM, CRM, and PCG. Input signals RD and IORQ are supplied to a NOR gate100 whose output is supplied to a NAND gate 214. The output from a NANDgate 102 having as its inputs signals PCG, CRM and GRM is supplied toNAND gate 214. Output VRMRD from NAND gate 214 is supplied to terminal Gof the flip-flop 23R.

Signals WR and IORQ are supplied as inputs to a NOR gate 101 whichsupplies an output signal to input terminal D of flip-flop 222. Clockpulse signal φ is inverted and supplied to the clock input terminal offlip-flop 222. Output signals DIR and DIR supplied to the flip-flop 23Wand data bus driver 33, respectively, from flip-flop 222 control thedirection of data flow in the read and write operations with respect toPCG-RAM 13.

A D-type flip-flop 221 has supplied at its input terminal CL the outputof a NAND gate 103 having as its inputs φ/2, φ, and 2φ. NAND gate 104having as its inputs φ2, φ, and 2φ supplies an output to terminal PR offlip-flop 221. The output signal from the flip-flop 221 controls thesignals to be supplied to data bus drivers 31, 32 and 33.

A NAND gate 105 has applied at its input terminals the signal φ and anoutput signal from terminal Q of flip-flop 221. The output of NAND gate105 is supplied as an input to NAND gates 106, 107 and 108. A NOR gate109 has inputs φ/2 and PCG and has its output supplied to NAND gate 106and a NAND gate 110. A NOR gate 111 having input signals φ/2 and CRMsupplies an output signal to NAND gate 107 and a NAND gate 112. A NORgate 113 has input signals φ/2 and GRM and supplies an output signal toNAND gate 108 and a NAND gate 114. A signal from output terminal Q offlip-flop 221 is supplied to the inputs of NAND gates 110, 112 and 114.NAND gate 106 supplies an output signal PCGS to the G terminal of databus driver 33. NAND gate 107 supplies output signal CRMS. NAND gate 108supplies output signal GRMS. NAND gate 110 supplies its output signalPCGWR to input terminal WE of PCG-RAM 13. NAND gate 112 supplies outputsignal CRMWR. NAND gate 114 supplies output signal GRMWR.

With reference to FIG. 4A, the Z80A-CPU of the exemplary embodiment hassix machine cycles M₁ to M₆ for the execution of a read or write datainstruction. The machine cycles use from three to six clock pulseperiods T₁ to T₆ of CPU 1. FIG. 4A illustrates machine cycle M₂ whichuses period T₁ to T₃, as indicated by the I/O address on address bus A₀to A₁₅. CPU 1 checks a signal WAIT during the T₂ state, and if it islow, the machine state remains in state T₂. State T_(w) indicates stateT₂ repeated by signal WAIT. As illustrated in FIG. 4B, signal φ/2 is 1/2the frequency of signal φ, and is in synchronism therewith.

FIG. 8 is a timing chart illustrating the operation of an embodiment ofthe present invention. FIG. 8A illustrates clock pulse φ/2 which is lowduring the period T_(c) and high during the period T_(d). During theperiod T_(c), the CPU 1 accesses video-RAM 10, while during periodT_(d), CRT controller 34 accesses video-RAM 10 in a DMA operation.

In FIG. 8B, the DMA address M_(i-1) is generated during periods T_(c)and T_(d). In the succeeding periods T_(c) and T_(d), the next addressM_(i) of signal VDA is generated.

Viewing FIGS. 8B, 8C, and 8D together, during the period T_(c), CPU 1occupies buses P₁, P₂, P₃ and P₄, as indicated in the figures by thedotted areas. During period T_(d), when CRT controller 34 accessesvideo-RAM 10, buses P₁ to P₄ carry address M_(i-1), as indicated in FIG.8B. In the next succeeding period T_(c), CPU 1 occupies buses P₁ to P₄,while CRT controller 34 occupies buses P₁ to P₄ with address M_(i) inthe next period T_(d).

During the period denoted by T_(c), the signal φ/2 is "L", and addressbuses 5H and 5L are connected through multiplexer 41 to address terminalAB of G-RAM 11 as well as through multiplexer 42 to address terminal ABof C-RAM 12, as shown in FIG. 8C and FIG. 2. As shown in FIG. 8D, databus 4 is connected through read-out and write-in ports 23W and 23R ofdata bus driver 23 and, through bus driver 31 and bus P₃ to dataterminal DB of G-RAM 11 and through bus driver 32 and bus P₄ to dataterminal DB of C-RAM 12. Accordingly, during the period T_(d), data ataddress M_(i-1) are read out from G-RAM 11 and C-RAM 12 by the DMAoperation.

As shown in FIG. 8E, at the end of each period T_(d), clock pulse signalCLK becomes "H", at which time, the data are latched to flip-flopcircuits 51 and 52 from G-RAM 11 and C-RAM 12, respectively.

As shown in FIGS. 8F, 8G and 8H, flip-flop circuits 51 and 52 and databuses P₅ and P₆ contain the address of data M_(i-2) during periods T_(c)and T_(d), which is one clock pulse behind data address M_(i-1) on busesP₁ to P₄.

The data from flip-flop circuit 51 are supplied to shift register 61,and, as seen in FIG. 8I, a shift/load signal S/L is supplied to shiftregister 61. When shift/load signal S/L is "L",the data are loaded inshift register 61. (Shift/load signal S/L goes to "L" when period T_(d)changes to period T_(c)). Shift register 61 is also supplied with shiftpulse SCLK at the start of each of the periods T_(c) and T_(d), as seenin FIG. 8J. Thus, as shown on FIG. 8K, register 61 produces the threeprimary color signals R, G and B and luminance signal L forming theupper 4-bits of the data latched during period T_(c). During the periodT_(d), shift register 61 produces the three primary color signals R, Gand B and a luminance signal L forming the lower 4-bits of the samedata, as hereinbefore described. The signals R, G, B and L are suppliedto multiplexer 63 for display on CRT 9.

During period T_(d), data from flip-flop circuit 52 and signals RA₀ toRA₂ forming part of DMA address signal VDA are supplied throughmultiplexer 43 to address terminal AB of PCG-RAM 13, whereby the dataare read out and delivered to shift register 62. Shift/load signal S/Land clock pulse signal CLK are also supplied to shift register 62, fromwhich the data are read out serially, as illustrated in FIG. 8L. Theserially read data are supplied to multiplexer 63 as hereinbeforedescribed. Consequently, multiplexer 63 produces on CRT 9 a threeprimary color signal by mixing the graphic plane with the characterplane of FIG. 6.

FIGS. 9A and 9B are timing charts illustrating the operation of CPU 1 inreading data from PCG-RAM 13. In FIG. 9A, period T₁ is synchronized withperiod T_(d), when clock pulse signal φ/2 2 is "H" and CRT controller 34accesses PCG-RAM 13. At the start of period T_(w), CPU 1 reads data fromPCG-RAM 13. Data read during period T₂ are supplied to data bus driver23R during the following period T_(w), as indicated by the arrow of FIG.9A between the graphs labeled P₆ and (23R).

In FIG. 9B, the machine states have shifted from T₁ =T_(d) to T₁ =T_(c).In periods T₁ and T_(w), clock pulse signal φ/2 is low, indicating thatCPU 1 occupies bus P₆ to access PCG-RAM 13.

FIGS. 10A and 10B illustrate the timing when CPU 1 writes data inPCG-RAM 13. In FIG. 10A, period T₁ is synchronized with period T_(d),while in FIG. 10B, period T₁ is synchronized with period T_(c).

In FIG. 10A, at the start of the period T_(w), the signal DIR drops downto latch the data from CPU 1 to flip-flop 23W. The data are supplied todata terminal DB of PCG-RAM 13 during period T₃ when signal PCGS is "L".

In FIG. 10B, clock pulse signal φ/2 is low during the period T_(w),indicating that data are written in PCG-RAM 13 by CPU 1 at that time.

According to the invention, random data cannot be accidentally writteninto PCG-RAM 13. Signal PCGS is not defined in the period T₁, so databus driver 33 has not been selected and the data address is not defined.Signal DIR is "H" during periods T₁ and T₂, so data bus driver 33 cannotoperate to write random data in video-RAM 10.

A Z80A-CPU has a set-up time of 50 n. sec., and a hold time of 0 n. sec.A set-up time for data according to the invention is calculated asfollows: ##EQU1## Since 97 n. sec. is greater than the set-up time of 50n. sec. for CPU 1, data stored in PCG-RAM 13 can be read out, asillustrated in FIGS. 9A and 9B.

Since a direct memory access is performed for video-RAM 10 in a timesharing manner, CRT 9 will not flicker. Video-RAM 10 is connected to theI/O address of CPU 1, so there is no decrease in the processing speed ofCPU 1 when a direct memory access for the display is performed forvideo-RAM 10. As shown in FIG. 4, the I/O address of the CPU 1 remainsthe same over more than three clock periods, i.e., over 750 n. sec.Accordingly, CPU 1 and CRT controller 34 each access the memory during a375 n. sec. period, and video-RAM 10 does not have to be a high speedRAM.

As shown in FIG. 1, ROM 2 and RAM 3 are assigned to respective memorycontrol areas of CPU 1, while video-RAM 10 is assigned to an I/O areathereof. In this manner, video-RAM 10 can be addressed by the BCregister pair of CPU 1 in response to I/O instructions. Accordingly, asa result of such allocation with respect to ROM 2, RAM 3 and RAM 10, theprogrammable or work area that can be used in RAM 3 is not reduced by avideo-RAM area so that a larger program area is provided for the user.Further, since the area of video-RAM 10 can be made as large as 32 Kbytes, a graphic function having high resolution, for example, 640×400dots, can be achieved. It is to be appreciated that the instructions orcommands given by CPU 1 for ROM 2 and RAM 3 can be similar to those usedin conventional microcomputer apparatus, while the I/O instructions orcommands can be easily used for video-RAM 10.

Operating instructions for a Z80A-CPU will now be discussed fortransferring data between an external I/O port 7 and CPU 1 (andconsequently, RAM 3). It is to be first noted that the Z80A-CPU includesat least A, B, C, D, E, H and L general purpose registers and thetransfer of 8-bit data between an external I/O port 7 and one or more ofthese registers occurs through data bus line 4. Corresponding addressinformation is transferred through the 16-bit address bus line comprisedof upper 8-bit address bus line 5H and lower 8-bit address bus line 5L.In particular, the following instructions can be used:

I-1 IN A, n

This instruction transfers 8-bit data at an input port designated bynumber n (n=0-255) to the A register of the CPU.

I-2 OUT n, A

This instruction transfers 8-bit data from the A register of the CPU toan output port designated by port number n. It is to be appreciatedthat, with these instructions, the 8-bit data from the A registerappears both on data terminals D₀ to D₇ and on address terminals A₈ toA₁₅. In such case, the lower 8-bit address terminals A₀ to A₇ aresupplied with address information and indicate the port number n.

II-1 IN r, (C)

This instruction transfers data at a port (identified by port number n)designated by the BC register pair to an r register, where the rregister is one of the A, B, C, D, E, H and L registers.

II-2 OUT (C), r

The instruction transfers data from the r register to the port(identified by port number n) designated by the BC register pair. Datafor the r register appears at data terminals D₀ to D₇, the C registercontains information from address terminals A₀ to A₇ corresponding tothe port number n, and the B register contains information from addressterminals A₈ to A₁₅ corresponding to the I/O device connected to thedesignated port. Since eight bits of information are provided in the Cregister, a maximum of 256 (0-255) I/O devices can be connected to eachport.

As will be apparent from the discussion hereinafter, the following blocktransfer instructions are also used with CPU 1:

III-1 INIR, INDR

With these instructions, a plurality of bytes of data, that is, a blockof data, can be transferred from a port n to the main memory. In suchcase, the BC register pair is used to determine the port number (Cregister) and the number of bytes to be transferred (B register). Thedata block is transferred to a memory location, the address of which isdetermined by the HL register pair. For example, the last addresslocation to which the data is to be transferred is stored in the HLregister pair. The B register is then used as a counter and counts downto zero. In particular, the value in the B register is continuouslydecremented by one, and during each decrement of one, one byte of theblock is transferred. When the value stored in register B is equal tozero, all of the bytes of the block of data have been transferred fromthe respective I/O port designated by the C register.

III-2 OTIR, OTDR

With these instructions, a data block can be transferred from the mainmemory to an I/O port designated by the C register. The HL register pairand the B register are used in a similar manner to that described above.

It is to be appreciated that the upper 8-bit address terminals A₈ to A₁₅are different from the I/O address terminals A₀ to A₇ of I/O port 7, sothat CPU 1 can distinguish between video-RAM 10 and I/O port 7.

Having described a specific preferred embodiment of the invention withreference to the accompanying drawings, it is to be understood that thepresent invention is not limited to that precise embodiment and thatvarious changes and modifications may be effected therein by one skilledin the art without departing from the scope or spirit of the inventionas described in the appended claims herein.

What is claimed is:
 1. A display memory access control system incombination with an asynchronous central processing unit providing mainmemory addresses and I/O addresses and including a master clock emittingclock pulses at a predetermined frequency, with each of said I/Oaddresses being provided for a duration greater than three cycles ofsaid clock pulses, comprising:main memory means addressable by said mainmemory addresses from said central processing unit; display randomaccess memory means for storing display data and being addressable bysaid I/O addresses from said central processing unit so that the workarea available for programs in said main memory means is not restrictedby the need to store display data; display means for displaying thedisplay data stored in said display random access memory means; displaycontroller means for generating addresses for DMA addressing of saiddisplay random access memory means; data bus means connecting saiddisplay random access memory means with said central processing unit andwith said display means; address bus means connecting said centralprocessing unit and said display controller with said display randomaccess memory means; multiplexing means interposed in said address busmeans and having a first state in which said I/O addresses from saidcentral processing unit are applied to said display random access memorymeans, and a second state in which said addresses generated by saiddisplay controller means are applied to said display random accessmemory means so that there is no decrease in the processing speed ofsaid central processing unit when providing direct access to saiddisplay random access memory means by said display controller means; andmultiplexing control means generating a control signal applied to saidmultiplexing means and having alternating first and second levelscorresponding to said first and second states, respectively, of saidmultiplexing means and which are cyclically repeated at a frequencywhich is one-half said predetermined frequency of the clock pulsesthereby avoiding the need for high speed operation of said displayrandom access memory means.
 2. The combination according to claim 1; inwhich said display means includes a cathode ray tube, and said addressesgenerated by said display control means are coordinated with scanning ofa roster in said cathode ray tube.
 3. The combination according to claim2; in which said display random access memory means includes a pluralityof random access memories for storing data corresponding to respectivelydifferent kinds of displays, each of said random access memories isallocated to a respective range of said I/O addresses, said multiplexingmeans includes a plurality of multiplexers interposed in said addressbus means for said plurality of random access memories, respectively,and being simultaneously changed between said first and second states inresponse to said first and second levels of said control signal, andsaid display means includes means for synthesizing display data readfrom said plurality of random access memories for display by saidcathode ray tube when said control signal is at said second level. 4.The combination according to claim 1; in which said central processingunit further includes an I/O port to which less than all of said I/Oaddresses are applied through said address bus means.
 5. The combinationaccording to claim 4; in which said I/O addresses include 16 bits, andonly the lower 8 bits are applied to said I/O port.
 6. The combinationaccording to claim 5; in which said lower 8 bits of the I/O addressesfrom said central processing unit are coupled through said address busmeans to the upper 8 bits of the addreses of said display random accessmemory means, and the upper 8 bits of said I/O addresses are coupled tothe lower 8 bits of the addresses of said display random access means.